MSC8113通路媒体网关的应用方案

Freescale 公司的MSC8113是高度集成的片上系统(SOC),它集成了三个StarCore® SC140内核,带硬件支持u/A律译码/编码的1024路时分复接(TDM),UART,16路DMA控制器,以太网控制器,1436KB SRAM以及灵活的系统接口单元(SIU),工作频率为300MHz 和400MHz,主要应用高宽带高度计算的DSP应用如无线代码转换,高密度分组电话DSP场(DSP fARM),以及高带宽的基站.本文介绍了三核处理器MSC8113的主要性能,方框图以及内核SC140的方框图,以及Freescale所提供的开发工具和672 G.711通路媒体网关的应用案
The MSC8113 device is a highly integrated system-on-a-chip that combines three StarCore® SC140 cores,1024-channel time division multiplexing (TDM) with hardware support for ?/A-law decoding/encoding, a UART, a 16-channel DMA controller, an Ethernet controller, 1436 Kbyte of SRAM, and a flexible system interface unit (SIU). The MSC8113 device targets high-bandwidth, highly computational DSP applications and is optimized for high-bandwidth wireless transcoding and a high-density packet telephony DSP farm, as well as high-bandwidth base station applications. The MSC8113 delivers enhanced performance while maintaining low power dissipation and greatly reducing system cost. The MSC8113 is provided in two frequencies: 300 and 400 MHz.
Each SC140 core has four ALUs and performs at a rate of up to 1200/1600 DSP million multiply and accumulate commands per second (MMACS) with an internal 300/400 MHz clock at 1.1 V. The MSC8113 delivers a total performance of 3600/4800 DSP MMACS. Each SC140 core connects to a level-1 224 Kbyte internal memory (M1) for program and data storage as well as a 16 Kbyte, 16-way instruction cache and a 4-entry write buffer queue for boosting core performance. All the SC140 cores share an internal 476
Kbyte level 2 memory (M2).
The TDM interface can transfer up to 1024 channels in and out of the device. The Ethernet controller port can be used for board-level interconnect and connection between boards. A full-featured multi-master 60x-compatible system port enables the SC140 cores to access external devices and gives an external host direct access to the internal memories. A flexible memory controller supports glueless accesses to various
memory devices on the system bus, including SDRAM, DRAM, SRAM, Flash memory, EPROM, and user-definable memory. An external host can also access the MSC8113 device directly through a 32/64-bit direct slave interface (DSI) port. A flexible 16-channel DMA controller transfers data to and from the core M1, the M2 memory, and the serial interfaces.

MSC8113 Tri-Core Digital Signal Processor
The MSC8113 is a highly integrated system-on-a-chip that combines three StarCore SC140 extended cores with an RS-232 serial interface, four time-division multiplexed (TDM) serial interfaces, thirty-two general-purpose timers, a flexible system interface unit (SIU), an Ethernet interface, and a multi-channel DMA controller. The three extended cores can deliver a total 3600/4800 DSP MMACS performance at 300/400 MHz.
Each core has four arithmetic logic units (ALUs), internal memory, a write buffer, and two interrupt controllers. The MSC8113 targets high-bandwidth highly computational DSP applications and is optimized for wireless transcoding and packet telephony as well as high-bandwidth base station applications. The MSC8113 delivers enhanced performance while maintaining low power dissipation and greatly reduces system cost.
The MSC8113 device is designed to provide an optimal solution for 3G wireless base stations, to help eliminate many of the costly and power hungry ASICs and FPGAs required in todays systems for both symbol rate and for chip rate assist. In addition, the MSC8113 device allows customers to add next-generation features that efficiently use available frequencies and higher bit rates in 3G systems.
Efficient application software development is key in Freescales strategy to expedite customers time-to-market. Developers can take advantage of development tools and real-time operating systems (RTOS) from Metrowerks, a Freescale company, and third-  suppliers. In addition Freescale is partnering with third-  vendors to provide integrated systems solutions that include GSM, CDMA, TDMA, and ITU G.7xx speech coders, hybrid echo cancellation, fax, modem, and xDSL software.
Three StarCore SC140 DSP extended cores, each with an SC140 DSP core, 224 Kbyte of internal SRAM M1 memory (1436 Kbyte total), 16 way 16 Kbyte instruction cache (ICache), four-entry write buffer, external cache support, programmable interrupt controller (PIC), local interrupt controller (LIC), and low-power Wait and Stop processing modes.
475 Kbyte M2 memory for critical data and temporary data buffering.
4 Kbyte boot ROM.
M2-accessible multi-core MQBus connecting the M2 memory with all three cores, operating at the core frequency, with data bus access of up to 128-bit reads and up to 64-bit writes, central efficient round-robin arbiter for core access to the bus, and atomic operation control of M2 memory access by the cores and the local bus.
Internal PLL configured are reset by configuration signal values.
60x-compatible system bus with 64 or 32 bit data and 32-bit address bus, support for multi-master designs, four-beat burst transfers (eight-beat in 32-bit data mode), port size of 64/32/16/8 bits controlled by the internal memory controller,.access to external memory or peripherals, access by an external host to internal resources, slave support with direct access to internal resources including M1 and M2 memories, and on-device arbitration for up to four master devices.
Direct slave interface (DSI) using a 32/64-bit slave host interface with 21–25 bit addressing and 32/64-bit data transfers, direct access by an external host to internal and external resources, synchronous or asynchronous accesses with burst capability in synchronous mode, dual or single strobe mode, write and read buffers to improve host bandwidth, byte enable signals for 1/2/4/8-byte write granularity, sliding window mode for access using a reduced number of address pins, chip ID decoding to allow one CS signal to control multiple DSPs, broadcast mode to write to multiple DSPs, and big-endian/little-endian/munged support.
Three mode signal multiplexing: 64-bit DSI and 32-bit system bus, 32-bit DSI and 64-bit system bus, or 32-bit DSI and 32-bit system bus, and Ethernet port (MII/RMII).
Flexible memory controller with three UPMs, a GPCM, a page-mode SDRAM machine, glueless interface to a variety of memories and devices, byte enables for 64- or 32-bit bus widths, 8 memory banks for external memories, and 2 memory banks for IPBus peripherals and internal memories.
Multi-channel DMA controller with 16 time-multiplexed single channels, up to four external peripherals, DONE or DRACK protocol for two external peripherals,.service for up to 16 internal requests from up to 8 internal FIFOs per channel, FIFO generated watermarks and hungry requests, priority-based time-multiplexing between channels using 16 internal priority levels or round-robin time-multiplexing between channels, flexible channel configuration with connection to local bus or system bus, and flyby transfer support that bypasses the FIFO.
Up to four independent TDM modules with programmable word size (2, 4, 8, or 16-bit), hardware-base A-law/?-law conversion, up to 128 Mbps data rate for all channels, with glueless interface to E1 or T1 framers, and can interface with H-MVIP/H.110 devices, TSI, and codecs such as AC-97.
Ethernet controller with support for 10/100 Mbps MII/RMII/SMII including full- and half-duplex operation, full-duplex flow controls, out-of-sequence transmit queues, programmable maximum frame length including jumbo frames and VLAN tags and priority, retransmission after collision, CRC generation and verification of inbound/outbound packets, address recognition (including exact match, broadcast address, individual hash check,
group hash check, and promiscuous mode), pattern matching, insertion with expansion or replacement for transmit frames, VLAN tag insertion, RMON statistics, local bus master DMA for descriptor fetching and buffer access, and optional multiplexing with GPIO (MII/RMII/SMII) or DSI/system bus signals lines (MII/RMII).
UART with full-duplex operation up to 6.25 Mbps.
Up to 32 general-purpose input/output (GPIO) ports.
I2C interface that allows booting from EEPROM devices.
Two timer modules, each with sixteen configurable 16-bit timers.
Eight programmable hardware semaphores.
Global interrupt controller (GIC) with interrupt consolidation and routing to INT_OUT, NMI_OUT, and the cores; twenty-four virtual maskable interrupts (8 per core) and three virtual NMI (one per core) that can be generated by a simple write access.
Optional booting external memory, external host, UART, TDM, or I2C.

600)this.style.width='600px';" border="0" />

图1.MSC8113方框图图1.MSC8113方框图

600)this.style.width='600px';" border="0" />

图2.StarCore SC140 DSP 扩展内核方框图

Freescale supplies a complete set of DSP development tools for the MSC8113 device. Our tools are focused on providing easier and more robust ways for designers to develop optimized DSP systems. Whether the application targets IP telephony or media gateways, the development environment gives the designers everything they need to exploit the advanced capabilities of the MSC8113 architecture.
The MSC8113 tool components include the following:
Integrated development environment (IDE). Easy-to-use graphical user interface and project manager for configuring and managing multiple build configurations.
C compiler with in-line assembly. The developer can generate highly optimized DSP code by exploiting the StarCore multiple-ALU architecture, with parallel fetch sets and high code density.
Librarian. The developer can create application-specific DSP libraries for modularity.
Linker. The developer can efficiently produce executables from object code and partition memory according to the application architecture; the linker supports code overlay.
Debugger. Seamlessly integrated real-time, non-intrusive, multi-mode and multi-DSP debugger handles highly optimized DSP algorithms. The developer can choose to debug in source code, assembly code, or mixed mode. Supports RTOS-aware debugger.
Royalty-free RTOS. Included with package.
Software Simulator. Full chip simulation; the developer can design an application and run it on the simulator before running it on the silicon. FCS integrated under IDE, the simulator provides customers with tools to create projects and debug them as they would on silicon.
Profiler. The developer can analyze and identify program design inefficiencies.
Data Visualization. Lets the developer graph variables, registers, regions of memory, and HSST data streams as they change over time. By changing the visualization filter, you can plot this data in a variety of ways; including line charts, logarithmic charts, polar coordinates, and scatter graphs.
High Speed Run Control. PowerTAP high speed host-target interface allows users to program in Flash memory, ROM, and cache.
Host Platform Support. Microsoft Windows and Solaris.
Development Board. The application development system (ADS).
Kit for MSC8113. A complete system for developing and debugging real-time hardware and software. The kit includes the MSC8113 device with a companion memory, JTAG debug interface,Ethernet interface, PCI interface, digital video interfaces and software device drivers.
Example Application: 672 G.711-Channel Media Gateway
The Media Gateway application shown in Figure 1 can process ~512 G.711 channels. The IP interface uses either UTOPIA or 100BaseT connected to the MSC8103 device that is the array aggregator. The MSC8113 performs the translation between the packet world and the PSTN world and the synchronous data is connected to the PSTN world through the TDM interface with a time slot assigner translating to protocols such as H.110 and MVIP. The MSC8103 DMA controller directly accesses the M1 and the M2 memories of the MSC8113 device through its local bus using its UPM. In parallel, it uses its system interface for accessing its SDRAM and flash. In this application 32-bit data DSI is sufficient, so the MSC8113 system bus can support up to 64-bit data. The user can use either a 32-bit wide SDRAM or two 32-bit SDRAM devices for storing channels and code, depending on the bandwidth need. The controller in this application is the MPC8260, and it accesses the MSC8103 HDI16 through its local bus while locating its memories on its system bus. Note that when premium voice is processed, each MSC8113 device performs fewer channels, so more devices can be connected to the MSC8103 device.

600)this.style.width='600px';" border="0" />

图3. 672 G.711通路媒体网关的应用案例方框图.