Altera视频串行数字接口(SDI)解决方案

Alteras Video Serial Digital Interface Solutions

Altera provides a range of complete solutions for the Serial Digital Interface (SDI) standard as defined by the Society of Motion Picture and Television Engineers (SMPTE). The solutions enable simple and fast protocol implementation, thereby reducing design risk, shortening development times and allowing you to concentrate on the core functions of the system design.

Integrated Solutions

By utilizing built-in transceivers to implement the protocol in a single device, Stratix II GX FPGAs provide a fully integrated SDI solution. The embedded transceivers are capable of auto-negotiation between the standard-definition SDI (SD-SDI) and the high-definition SDI (HD-SDI) data rates on a single transceiver. Table 1 gives an overview of the Stratix II GX device SDI solution.



SD-SDI Solutions (Non-transceiver)
For high-volume, cost-sensitive SD-SDI applications Cyclone® II FPGAs,  combined with the Altera SDI Megafunction, provide the ideal solution. The Cyclone II FPGA I/O can directly support the protocol using low-voltage differential signaling (LVDS) I/Os, which fits perfectly for the data rate requirement of SD-SDI. Equally, Stratix II FPGAs or HardCopy® II structured ASICs can be used in applications requiring the highest density and performance, using the same class of I/O.
Technology Background
The SDI standard is defined by SMPTE, and is widely used in broadcasting and video production. The SDI standard describes how to carry uncompressed serial, digitized video data between equipment in production facilities over video coax cables. There are two variations of the SDI standard, based on the data rate: SD-SDI and HD-SDI. The basic electrical specifications of these two variations are the same, but the main difference is that HD-SDI has higher data rate at 1.485 Gbps while SD-SDI data rate ranges from 143 Mbps to 540 Mbps, with 270 Mbps being the most popular rate.
Altera’s SDI solutions include advanced FPGA architectures, hardware-verified IP and reference designs, application notes, demonstration boards, and board design datasheets.  Altera is focused on giving digital broadcast equipment manufacturers a competitive edge and has developed the expertise in video production and video delivery industry. By using Alteras SDI solutions, you can integrate discrete components and multiple channels into a single FPGA, substantially reducing system costs and accelerating time-to-market.
Altera Video Over IP Reference Design
Introduction
The Altera® video over IP reference design demonstrates transmission of MPEG-2 transport stream (TS) data over internet protocol (IP)-based networks. The reference design bridges one or more compressed video streams and IP packets carried over 100 megabits per second (Mbps) or 1 gigabit per second (Gbps) Ethernet.
The reference design accepts TS data and encapsulates it for transmission over Ethernet when functioning as a TS-to-Ethernet bridge (Figure 1). Using the Ethernet-to-TS Bridge function (Figure 2), the design can also receive frames from Ethernet and generate TS data.
Figure 1. TS-to-Ethernet Bridge



Figure 2. Ethernet-to-TS Bridge



The TS interface supports 188- and 204-byte packets as standardized for digital video broadcasting (DVB) MPEG-2 transport. The reference design supports both multi-program TS (MPTS) and single-program TS (SPTS) data. The reference design does not attempt to identify or separate individual programs from an MPTS input.
The Altera Asynchronous Serial Interface (ASI) Reference Design can connect the TS interface to a DVB-ASI.
Encapsulation of the TS data for Ethernet uses IP and the user datagram protocol (UDP). Optionally, the real-time transport protocol (RTP) can also be used. Dedicated hardware performs the encapsulation, which maximizes the throughput of the reference design and minimizes latency. Frames can be processed, transmitted, and received at the Ethernet line rate, which supports an aggregate TS bandwidth of over 900 Mbps for a gigabit Ethernet link.
For multiple TS interfaces, the reference design individually maps each one to a specific UDP/IP socket (a combination of IP address and UDP port). All other encapsulation parameters can also be individually configured per TS.
The reference design includes a Nios® II processor. Software running on the processor configures the operation of the reference design and manages any Ethernet traffic.

Features

TS-to-Ethernet bridge
Ethernet-to-TS bridge
Video transport at Ethernet line rates (100/1000 Mbps)
Dedicated hardware for line speed UDP/IP encapsulation & packet classification, with optional RTP support
Software support for management protocols on the Nios II processor
Parallel TS interface and ASI connectivity
Related Links
AN 344: ASI Reference Design

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