NiosII汽车导航系统开发方案

The automotive industry is taking a close look at programmable logic devices (PLDs) and how they can contribute to the success of both system suppliers and automakers (original equipment manufacturers). With a lowering cost structure and increasing system performance, PLDs are entering the mainstream automotive market. Unlike ASSP solutions, PLDs provide flexibility that is an ever increasing requirement in the automotive industry.

PLDs, which have already found a home in the infotainment and communications markets, are included in designs for the emerging driver assistance automotive segment. This segment consists of some of the fastest growing applications, including lane departure warning, night vision, and tire pressure monitoring. With a low silicon cost structure, abundance of intellectual property (IP) cores, reference designs, and a long product shelf life, PLDs are an ideal choice for the growing automotive electronics market.
Automotive electronics such as navigation systems, rear seat entertainment systems, and game consoles are increasingly integrated in new cars, but these consumer applications require a significant amount of graphics processing. Additionally, lane departure warning systems and night vision systems also involve a large amount of graphics processing. New technology is making it possible to have the same high-level graphic quality in your car as you do in your home theater.

FPGAs are redefining this new technology and making it feasible to implement electronic systems that can provide the highest graphics processing capabilities. The advantage of Altera® FPGAs is that they can provide a far more flexible solution than simple interfacing between the microprocessor and the multiple consumer interface standards. The FPGA architecture allows for extremely efficient high-speed data routing. Processing of this data can occur in parallel within the digital domain in the FPGA rather than moving it to an external microprocessor for serial operation.

Navigation Systems
A navigation system is one of the key applications within the automotive space that utilizes a fair amount of graphics processing. The graphics processing complexity varies from a simple turn-by-turn (TBT) navigation to a more sophisticated 3D navigation system.  Figure 1 shows a typical block diagram of a navigation system. The architecture consists of a host CPU (which is generally a Hitachi SH4, Motorola Power PC, or a TI OMAP processor) with a graphics processor. Various peripherals talk to these processors, including keyboards and thin-film transistor (TFT) displays.

Figure 1.  Typical Navigation System

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Graphics processing requires the computation of numerous algorithms such as scaling, filtering, and alpha blending. Unlike digital signal processors or ASSPs, FPGAs are better suited to perform these computationally-intensive algorithms because they can handle multiple instructions in a single clock cycle.

Figure 2 shows a low-cost graphics implementation. The video-in can be a BT.656 input (YUV 4:2:2), with color space converter (CSC) to output RGB. The memory interface to the Avalon® switch fabric allows high graphic computations to be accommodated. Memory types that are supported include: single data rate (SDR), double data rate (DDR), and DDRII. The Altera Nios® II 32-bit embedded processor is primarily used for graphics processing (line draw, frame creation) and provides additional control functions. Graphics hardware acceleration can include functions such as BitBlt (copy object into frame buffer, 2D-DMA transfer, possibly with blending). Alpha blending can have multiple channels. The Cyclone® FPGA series is capable of supporting LVDS graphics output for remote display applications.

Figure 2. Low-Cost Graphics Implementation

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Alteras Nios II Development Kit, Stratix II Edition provides a complete development environment, including everything hardware and software designers need for system-level designs. Based on the Nios II family of embedded processors and the Stratix II EP2S60 device, youll find the kit is ideal for designing and prototyping a wide range of embedded applications.
The Nios II Development Kit, Stratix II Edition includes:
Nios II Embedded Design Suite, including
Nios II integrated development environment (IDE) and debugger
GNU tools
Nios II instruction set simulator (ISS)
MicroC/OS-II real-time operating system evaluation
NicheStack TCP/IP Network Stack, Nios II Edition evaluation
Nios II C-to-Hardware Acceleration Compiler evaluation
Nios II processor intellectual property (IP) cores
Quartus II design software, including:
SOPC Builder system development tool
Library of standard microprocessor peripherals
One-year license, Windows platform only
RoHS-compliant development board (shown in Figure 1), featuring:
Stratix II EP2S60F672C3 device
MAX EPM7128AE CPLD configuration control logic
1-Mbyte synchronous SRAM
16-Mbyte DDR SDRAM
16-Mbyte flash memory
EPCS64 serial configuration device (64 Mbit)
CompactFlash connector header for TypeICompactFlash cards (40 available user I/O pins)
10/100 Ethernet physical layer/media access control (PHY/MAC)
Ethernet connector (RJ-45)
One serial connector (RS-232 DB9 port)
Two expansion/prototype headers (2 x 41 available user I/O pins)
JTAG connectors for FPGA and CPLD
Mictor trace/debug connector
One set PMC headers (32-bit)
Four user-defined push-button switches
Eight user-defined LEDs
Dual seven-segment LED display
Power-on reset circuitry
10/100/1000 PHY Daughter Board with Marvell 88E1111 Ethernet PHY Device from MorethanIP
OpenCore Plus evaluation of the Altera Triple-speed Ethernet IP Core and supporting design example
Cables and accessories
USB-Blaster? download cable
Serial cable (RS-232)
9-V power supply
International power cords
LCD module
Ethernet (RJ45) cable (7 feet)
Ethernet crossover adapter
Many hardware and software reference designs  
One-year subscription to Nios II Embedded Design Suite upgrades
This subscription does not include Quartus II software updates. The Altera®Software Subscription includes the Quartus II design software.

There are no license or royalty fees required to develop with Nios II processors in Altera FPGAs and HardCopy devices.
Coupon for a 20 percent discount on any one instructor-led Altera Technical Training course scheduled in North America
Figure 1. Nios II Development Board, Stratix II Edition

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