cadence 16.5 将于5月23日发布

http://www.cadence.com/cadence/n ... /Pages/allegro.aspx
New Allegro 16.5 Technology

On May 23, 2011 Cadence will release the 16.5 version of its Allegro PCB and IC packaging technology, providing customers with new capabilities for a shorter, predictable, and convergent path to product creation. The latest Allegro technology will be available through flexible on-demand product configurations that offer cost-efficiency and scalability. Allegro 16.5 spans silicon, SoC, and system-level development and offers PCB designers benefits such as:

* Higher functional density with a constraint-driven flow for embedded components
* Faster timing closure with new PCB interconnect design planning technology
* Fewer physical prototype iterations with concurrent team design authoring
* More efficient low-power design with integrated power delivery network analysis
* A compliant and faster implementation path with package/board-aware SoC IP
* Smoother collaboration among global teams with new SiP distributed co-design
* Flexibility through “base plus options” configurations