堵住电流泄漏：摩尔定律在晶体管发展中继续有效

　　受到物理限制，电子工程师必须构想出更加精巧的晶体管
   
   　　1965年，戈登·摩尔预言，在一定大小的芯片上所能容纳的晶体管的数量每两年就会增加一倍，这就是所谓的摩尔定律。多年来这个定律一直在发挥作用。第一个集成电路（由德州仪器的杰克·基尔比发明，见图）还只是一个笨拙不堪的大家伙，而现在晶体管已需用纳米（1米的十亿分之一）来计量。人们以摩尔定律的发展速度创造了快速而智能化的计算机，图案漂亮并将世界联接在了一起。从摩尔博士创立这个定律的时候起，人类就进入了一个不可思议的信息技术时代。本来一个不经意的发现竟有如此强大的生命力。
   　　其实它并不是一条真正的定律，而只是一种现象，一种对技术发展漫漫征程的描述，发展的每一步都包含着具体的技术变革（见图表）。技术发展势不可挡，已成预言般的信条。晶体管的每一次“缩身”，都是朝着它们的最小尺寸迈进了一步。如果按此定律继续发展， 20年之内，晶体管将会与几个单晶硅原子大小相当。
   　　说得更精确一点，晶体管已经很小很小，在这样大小的空间中每个原子都变得举足轻重。原子太少它们之间的绝缘性消失，或者因 “量子隧穿”现象（一种电子自然消失、并在他处重现的现象）将电流泄漏到本不该流向的地方。不适当种类的原子太多效果同样不妙，这会影响晶体管的导电性。因此工程人员正在努力重新设计晶体管。这样看来，摩尔的预言在未来的一段时间里还将继续有效。
   
   　　
   
   　　原子核母板
   
   　　晶体管实际上是一个电子控制的转换器，它由4部分组成：源极（电流从该极流入），漏极（电流从这里流出），（连接源极和漏极的）沟道以及栅极（通过电压的变化控制通道的开关）。在传统的晶体管中，这些组件都分布在同一个平面上。要防止漏电，一种思路就是把晶体管改为三维设计。
   　　制造一个从母体芯片上伸出来的晶体管可以使许多组成原子的布置更加有效，特别是那些构成了通道和栅极的原子。将通道外伸、三面围以栅极原子，这样就能够增加栅极的表面积，更好地控制通道，并减少泄漏。在导通状态下，晶体管栅极的功能越是优良，通过的电流就越大。
   　　五月份，美国着名的芯片巨头英特尔（摩尔博士也是该公司创建人之一）宣布一项计划，对这种营销时冠以“三栅极”的技术设备进行商业性开发。公司预计，新晶体管将于今年晚些时候面世，这种晶体管比现有的晶体管省电一半，特别适合于笔记本电脑使用，毕竟，电池寿命是笔记本电脑的一大卖点。
   　　全面改用三维模式，这在一个成熟的行业内很难推广，毕竟他们的二维模式已经成熟。包括美国公司Globalfoundries、英国公司ARM在内的绝缘硅联合会，试图把提高平板晶体管作为他们的一个替代方案，该联合会的技术是把在一个纯硅片薄层内部制作晶体管，这层纯硅下面是一个绝缘层，再下面是一个标准晶片，这个标准晶片被用作基底，用来安放晶体管。这种方法要把晶体管的沟道做得足够薄，使栅极产生的电磁场能够透过整个沟道，提高栅极所能发挥的最大控制力。但这种方法迫使绝缘硅联合会必须面对晶体管尺寸不断缩小而产生的第二个问题：偏离正常位置的原子要么太多，要么太少。
   　　为了改善电子性能，制造晶体管所用的硅材料中常需掺入其他元素 。最新的晶体管尺寸非常小，在其沟道中掺杂只要往硅中注入少量杂质原子，如果这个量掌握得不好，晶体管的正常运行就会受到影响。但制造过程中的偏差使得这种要求很难达到。绝缘硅联合会希望使用的超薄沟道掺入杂质的工艺极其困难，因此，他们决定不向硅中掺入杂质，而用纯净硅来制造晶体管的沟道。但这要求硅层厚度不能超过5纳米。而且在整个晶片上这个厚度几乎要保持一致，英特尔公司（应当承认，它并不是一个心平气和的旁观者）认为，如此精准的标准，肯定会增加晶体管的制造成本。
   　　SuVolta是硅谷的一家小公司，他们提出了另一种方法。他们计划制造的平板晶体管通道也不掺入杂质。但这家公司打算使用价格低廉的传统硅晶片，而不必改变晶片的成分，不必制造绝缘硅联合会要求的超薄沟道，他们的过人之处在于，在沟道的下面增加一个栅极。两个栅极共同作用就能够控制没有添加杂质并且厚度不够小的沟道。就这样，功能更好而能耗更低的晶体管就产生了，该公司表示，它的能耗减少到只有传统类型的晶体管能耗的一半，而性能上并没有损失。SuVolta此举激起了日本电子巨头富士通的极大兴趣，目前他们已拥有这项技术的生产许可。
   
   　　还有多少发展空间
   
   　　所有这些方法都意味着摩尔定律至少在未来几年内还会继续发挥作用。数百位专家每年都要对半导体国际技术路线图进行更新。他们预测，标准晶体管的横向尺寸到2013年将减小到16纳米（现在是32纳米），到2015年还将减小到11纳米。要想进一步缩小就需要一个概念上的飞跃。有幸的是，已经有了几个这样的选择。
   　　一个最有前景的方法去年已由考林吉带领的爱尔兰廷德尔国家研究所描绘出来。他们发表一篇论文，宣布他们已经创造出无接晶体管。这一方法早在1925年就由一位名叫朱利叶斯·利林菲尔德的物理学家获得专利，但直到现在，它的制造依然是个难题。
   　　晶体管连接处的两面是掺入了导电电子（因为电子带有负（negative）电荷，因此被称为n型材料）的硅片，而p型区域的晶格中掺入了带有正电的空穴，这些空穴由电子的游离而产生。还有一些三极管，源极和漏极都是p型，沟道是n型。在其他情况下，情况正好相反。在n型和p型的结合处，硅的作用就像一个阀门，防止电流流向相反的方向。
   　　然而，晶体管越小，制造PN结的难度就越大，这也是受到了掺入元素浓度波动的影响。考林吉博士的设计—-类似英特尔的三栅极，在一个单独的、超薄的硅导线周围环绕一个三维栅极--为避免这种情况，整个晶体管全部采用一种比常规平板晶体管所用的半导体掺入元素浓度更大的半导体来制造。设计中含有一个极薄的沟道，就像阀门一样，断路时载流子（比如，自由电子或空穴）全部消失，通路时充满这种载流子。它的尺寸同样应该可以缩小。廷德尔研究院的研究人员去年报告说，通过对这种原子排列的无接晶体管进行计算机模拟显示他们的运行状况完好，而且它的栅极长度只有3.1纳米。
   　　这种栅极长度会使摩尔定律在未来几年将继续发挥作用，此后，摩尔定律要想继续发挥作用，就要求有更多的创新思维。比如，大量的学术人员和工程人员正在思考，如何制造出这样一种晶体管，使得量子沟道成为一种特色，而不是一种缺陷。根据量子理论，电子只有在某个能量级才能获得，这就意味着利用隧穿效应的晶体管可能直接从从弱电流转至强电流，并且不要预热时间。
   　　这也许是一个不错的想法。晶体管的大小受到单原子大小的局限，在这种情况下，还不知这是否就是工程人员最后一个即兴之举。当摩尔博士宣布这一定律时，他本以为定律可能会在10年内有效。具有不可抗拒力量的人类创造力确保摩尔定律的寿命比预想的大大延长了，但这种力量现在正面临着原子物理学难以逾越的障碍。这真是一场引人入胜的竞赛。(编译：Kevin)
   
   附原文：Plugging the leaks
   
   As physical limits bite， electronic engineers must build ever cleverer transistors
   Aug 20th 2011 | from the print edition
   MOORE’S LAW-the prediction made in 1965 by Gordon Moore， that the number of transistors on a chip of given size would double every two years-has had a good innings. The first integrated circuit （invented by Jack Kilby of Texas Instruments， see above） was a clunky affair. Now the size of transistors is measured in billionths of a metre. Moore’s law has yielded fast， smart computers， with pretty graphics and worldwide connections. It has thereby ushered in an age of information technology unimaginable when Dr Moore coined it. Not bad going for what was originally just an off-the-cuff observation.
   That observation， however， is not truly a law. It is， rather， the description of a journey of many steps， each a specific technological change （see chart below）。 That new steps will happen is as much an article of faith as a prediction. Every time transistors shrink， they get closer to the point where they can shrink no further-for if the law continues on its merry way， transistors will be the size of individual silicon atoms within two decades.
   More to the point， they have already shrunk to a size where every atom counts. Too few atoms can cause their insulation to break down， or allow current to leak to places it is not supposed to be because of a phenomenon called quantum tunnelling， in which electrons vanish spontaneously and reappear elsewhere. Too many atoms of the wrong sort， though， can be equally bad， interfering with a transistor’s conductivity. Engineers are therefore endeavouring to redesign transistors yet again， so that Dr Moore’s prediction can remain true a little longer.
   Atom heart motherboard
   A transistor is an electrically operated switch composed of four pieces： a source （where current enters）， a drain （where it leaves）， a channel （which links the two） and a gate （which opens and shuts the channel by varying in voltage）。 In a conventional transistor， these components lie in about the same plane. One idea for dealing with leaks is to change that by moving transistor design into three dimensions.
   Building a transistor that sticks out of its parental chip lets many of its component atoms be deployed more usefully-particularly those that constitute the channel and the gate. By sticking the channel into the air and surrounding it on three sides with the atoms of the gate， you increase the surface area of the gate. That gives better control of the channel and reduces leaks. Having a better-functioning gate also lets more current flow when the transistor is on.
   In May Intel， an American chip giant （co-founded， as it happens， by Dr Moore）， announced plans to commercialise a technological fix of this sort under the marketing name “Tri-Gate”。 The company reckons the new transistors， which should be available later this year， will consume half as much power as its existing offerings， making them particularly suitable for mobile computing， where battery life is an important selling point.
   A universal change to three dimensions， though， will be difficult to sell to an industry that has grown up thinking in two. As an alternative the Silicon On Insulator （SOI） consortium， which includes Globalfoundries， an American firm， and ARM， a British one， is trying to improve flat transistors. The consortium’s technology builds its transistors inside a sliver of pure silicon， laid on top of an insulator， which in turn sits on top of a standard wafer， the substrate on which transistors are constructed. The idea is to make the channel as thin as possible， allowing the electric field generated by the gate to penetrate the entire thing， thus improving the control that the gate is able to exert. But this approach also forces the consortium to tackle the second problem raised by the continual shrinkage of transistors： too many or too few atoms in the wrong places.
   The silicon of which transistors are made is frequently doped with other elements， to affect its electrical properties. The latest devices， though， are so small that doping their channels involves placing just a handful of dopant atoms among the silicon. Get the number wrong， and things will not work properly. But fluctuations in the manufacturing process make the required consistency hard to achieve. Correctly doping the ultra-thin channels that the consortium hopes to use is simply too difficult-hence the decision to do without dopants altogether and build channels out of pure silicon. But the design requires that this silicon layer be no more than five nanometres （billionths of a metre） deep. That figure， moreover， must be almost constant across the entire wafer-an exacting standard which Intel （admittedly， not a dispassionate observer） believes will add to manufacturing costs.
   SuVolta， a small company in Silicon Valley， has therefore come up with a third approach. It， too， plans to build flat transistors with undoped channels. But it will do so on conventional， cheap silicon wafers without the need for the modified wafers or ultra-thin channels required by the SOI consortium， a trick it accomplishes by adding a second gate beneath the channel. In concert， the two gates are able to control the undoped channel without its having to be ridiculously thin. Once again， the result is better-behaved transistors and reduced power consumption-as little as half that demanded by old-style transistors， says the firm， with no loss of performance. SuVolta has already piqued the interest of Fujitsu， a Japanese electronics giant， which has licensed the technology.
   Room at the bottom
   All these approaches mean that Moore’s law should be able to chunter along for a few more years， at least. The International Technology Roadmap for Semiconductors， which is updated every year by a team of several hundred experts， predicts that standard transistors will be 16 nanometres across by 2013 （at the moment， 32 nanometres is the standard） and 11 nanometres by 2015. To go smaller than this， though， will require yet another conceptual leap. Fortunately， there are several on offer.
   One promising approach was outlined last year by a team at the Tyndall National Institute in Ireland， led by Jean-Pierre Colinge. They published a paper announcing the creation of a junctionless transistor-an idea patented in 1925 by a physicist called Julius Lilienfeld， but which was， until recently， too difficult to manufacture.
   The junctions in a transistor are between bits of silicon doped to conduct electrons （known as n-type material， because electrons are negatively charged）， and p-type areas doped to conduct positively charged holes in the crystal lattice， which are places where electrons should be， but aren’t. In some transistors， source and drain are p-type， and channel n-type. In others the reverse is true. The junctions between n- and p-type silicon act like valves， stopping current flowing in the wrong direction.
   As transistors get smaller， however， laying down n-type and p-type materials in proximity gets harder， thanks once again to fluctuations in the concentrations of dopants. Dr Colinge’s design-which， like Intel’s Tri-Gate， clamps a 3D gate around a single， ultra-thin silicon wire-avoids this by building the entire device from a single type of semiconductor， with much higher dopant concentrations than a conventional flat transistor. The design incorporates a channel thin enough to become entirely devoid of carriers （ie， free electrons or holes） when switched off， thus acting as a valve， yet full of them when switched on. It should be shrinkable， too. The Tyndall Institute’s researchers reported last year that atom-by-atom computer simulations of junctionless transistors with a gate length of just 3.1 nanometres show that they ought to work perfectly.
   Such a gate length would keep Moore’s law rolling for several years. To carry on beyond that， however， requires even more exotic thinking. A number of groups of academics and engineers， for example， are pondering how to make transistors in which quantum tunnelling is a feature rather than a bug. Quantum theory dictates that electrons are available only at certain energy levels， which means that a transistor which harnessed the tunnelling effect could switch directly from a low current （off） to a high current （on）， with no ramp-up time.
   That would be a neat trick. Whether it would be the last one up the engineers’ sleeves， as the single-atom limit looms， remains to be seen. When he first promulgated it， Dr Moore thought his law might endure for ten years. The irresistible force of human ingenuity has ensured it has done far better than that. But that force is now up against the immovable object of atomic physics. It is a fascinating contest.